
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   14:29:56 04/23/2012
-- Design Name:   flags
-- Module Name:   C:/Xilinx92i/flags/testbench_flags.vhd
-- Project Name:  flags
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: flags
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY testbench_flags_vhd IS
END testbench_flags_vhd;

ARCHITECTURE behavior OF testbench_flags_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT flags
	PORT(
		int_ZF : IN std_logic;
		int_CF : IN std_logic;
		alu_ZF : IN std_logic;
		alu_CF : IN std_logic;
		enable : IN std_logic;
		clk : IN std_logic;
		reset : IN std_logic;
		is_end_interrupt : IN std_logic;          
		CF : OUT std_logic;
		ZF : OUT std_logic
		);
	END COMPONENT;

	--Inputs
	SIGNAL int_ZF :  std_logic := '0';
	SIGNAL int_CF :  std_logic := '0';
	SIGNAL alu_ZF :  std_logic := '0';
	SIGNAL alu_CF :  std_logic := '0';
	SIGNAL enable :  std_logic := '0';
	SIGNAL clk :  std_logic := '0';
	SIGNAL reset :  std_logic := '0';
	SIGNAL is_end_interrupt :  std_logic := '0';

	--Outputs
	SIGNAL CF :  std_logic;
	SIGNAL ZF :  std_logic;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: flags PORT MAP(
		int_ZF => int_ZF,
		int_CF => int_CF,
		alu_ZF => alu_ZF,
		alu_CF => alu_CF,
		enable => enable,
		clk => clk,
		reset => reset,
		is_end_interrupt => is_end_interrupt,
		CF => CF,
		ZF => ZF
	);

	clk_tb: PROCESS
	BEGIN
		wait for 50 ns;
		clk <= '1';
		wait for 50 ns;
		clk <= '0';	
	END PROCESS;
	
	tb : PROCESS
	BEGIN
		reset <= '1';
		wait for 10 ns;
		reset <= '0';
		enable <= '1';
		is_end_interrupt <= '0';		
		int_CF <= '1';
		int_ZF <= '1';
		alu_CF <= '0';
		alu_ZF <= '0';
		wait for 100 ns;
		is_end_interrupt <= '1';
		wait for 100 ns;
		is_end_interrupt <= '0';
		wait for 100 ns;
		is_end_interrupt <= '1';
		wait for 100 ns;
		is_end_interrupt <= '0';
		wait for 100 ns;
		is_end_interrupt <= '1';
		wait for 100 ns;
		is_end_interrupt <= '0';
		wait for 100 ns;
		is_end_interrupt <= '1';
		wait for 100 ns;
		is_end_interrupt <= '0';
		wait; -- will wait forever
	END PROCESS;

END;
